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ST7MC1K2-Auto 数据表(PDF) 105 Page - STMicroelectronics

部件名 ST7MC1K2-Auto
功能描述  Clock, reset and supply management
PDF  371 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7MC1K2-Auto 数据表(HTML) 105 Page - STMicroelectronics

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ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
On-chip peripherals
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10.3.3
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
Counter register (CR)
Counter high register (CHR) is the most significant byte (MSB).
Counter low register (CLR) is the least significant byte (LSB).
Alternate counter register (ACR)
Alternate counter high register (ACHR) is the MSB.
Alternate counter low register (ACLR) is the LSB.
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
status register, (SR), (see16-bit read sequence (from either the counter register or the
alternate counter register) on page 107).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in
the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and
PWM mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 51. The value in the counter register repeats every 131 072, 262 144 or 524 288 CPU
clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4,
fCPU/8 or an external frequency.
Obsolete
Product(s)
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