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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7MC1K2-Auto 数据表(PDF) 323 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 323 Page - STMicroelectronics |
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323 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto Electrical characteristics 323/371 12.5.4 Clock security system with PLL Table 201. PLL characteristics Symbol Parameter Min Typ Max Unit fOSC PLL input frequency range 7 8 MHz Output frequency Output frequency when the PLL attains lock 16 MHz tLock PLL lock time (Locked = 1) 50 100 µs Jitter Jitter in the output clock 2 % fCPU CPU clock frequency when VCO is connected to ground (ICD internal clock or back up oscillator) 3MHz Table 202. Clock detector characteristics Symbol Parameter Min Typ Max Unit fDetect Detected minimum input frequency 500(1) 1. Data based on characterization results, not tested in production. kHz tsetup Time needed to detect OSC1 (or OSCIN) once CKD is enabled 3µs thold Time needed to detect that OSC1 (or OSCIN) stops 3µs Obsolete Product(s) - Obsolete Product(s) |
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