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ST7MC1K2-Auto 数据表(PDF) 338 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 338 Page - STMicroelectronics |
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338 / 371 page  Obsolete Product(s) - Obsolete Product(s) Electrical characteristics ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 338/371 Figure 150. SPI Master timing diagram(1) 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration. SS INPUT CPHA = 0 MOSI OUTPUT MISO INPUT CPHA = 0 CPHA = 1 CPHA = 1 tc(SCK) tw(SCKH) tw(SCKL) th(MI) tsu(MI) MSB IN MSB OUT BIT6 IN BIT6 OUT LSB OUT LSB IN See note 2 Seenote2 CPOL = 0 CPOL = 1 CPOL = 0 CPOL = 1 tr(SCK) tf(SCK) th(MO) tv(MO) Obsolete Product(s) - Obsolete Product(s) |
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