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AT83C5111 数据表(PDF) 12 Page - ATMEL Corporation |
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AT83C5111 数据表(HTML) 12 Page - ATMEL Corporation |
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12 / 86 page  12 AT8xC5111 4190A–8051–11/02 Clock Prescaler Register This register is used to reload the clock prescaler of the CPU and peripheral clock. Table 4. CKRL - Clock Prescaler Register (97h) Reset value = 1111 1111b Not bit addressable Clock Control Register This register is used to control the X2 mode of the CPU and peripheral clock. Table 5. CKCON0 Register (8Fh) 765 43210 M Bit Number Bit Mnemonic Description 7: 0 CKRL 0000 0000b: Division factor equal 512 1111 1111b: Division factor equal 2 M: Division factor equal 2*(256-M) 765 43210 - WdX2 PcaX2 SiX2 - T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7- Reserved 6WdX2 Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5PcaX2 Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4SiX2 Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3- Reserved 2T1X2 Timer 1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle 1T0X2 Timer 0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. |
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