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AT83C5111 数据表(PDF) 13 Page - ATMEL Corporation |
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AT83C5111 数据表(HTML) 13 Page - ATMEL Corporation |
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13 / 86 page  13 AT8xC5111 4190A–8051–11/02 Reset value = X000 0000b Not bit addressable Table 6. CKCON1 Register (AFh) Reset value = XXXX XX00b Not bit addressable 0X2 CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits. 7 6 5 43210 - - - --- BRGX2 SPIX2 Bit Number Bit Mnemonic Description 7- Reserved 6- Reserved 5- Reserved 4- Reserved 3- Reserved 2- Reserved 1BRGX2 BRG clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 0 SPIX2 SPI clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Bit Number Bit Mnemonic Description |
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