AT83C5111 datasheet(37/86 Pages) ATMEL

37 / 86 page

AT8xC5111

4190A–8051–11/02

Figure 3. Full-Duplex Master-slave Interconnection

Master Mode

The SPI operates in Master mode. Only one Master SPI device can initiate transmis-

sions. Software begins the transmission from a Master SPI module by writing to the

Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is imme-

diately transferred to the shift register. The byte begins shifting out on MOSI pin under

the control of the serial clock, SCK. Simultaneously, another byte shifts in from the

Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral

transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes

set, the received byte from the Slave is transferred to the receive data register in

SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA)

with the SPIF bit set, and then reading the SPDAT.

When the pin SS is pulled down during a transmission, the data is interrupted and when

the transmission is established again, the data present in the SPDAT is present.

Transmission Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity

using two bits in the SPCON: the Clock POLarity (CPOL (1)) and the Clock PHAse

(CPHA(1)). CPOL defines the default SCK line level in idle state. It has no significant

effect on the transmission format. CPHA defines the edges on which the input data are

sampled and the edges on which the output data are shifted (Figure 15 and Figure 16).

The clock phase and polarity should be identical for the Master SPI device and the com-

municating Slave device.

Figure 4. Data Transmission Format (CPHA = 0)

8-bit Shift register

SPI

Clock Generator

Master MCU

8-bit Shift register

MISO

MOSI

SCK

VSS

VDD

Slave MCU

Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

Capture Point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (Internal)

SCK Cycle Number

AT83C5111 数据表(PDF) 37 Page - ATMEL Corporation

AT83C5111 数据表(HTML) 37 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

数据表下载