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AT83C5111 数据表(PDF) 65 Page - ATMEL Corporation |
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AT83C5111 数据表(HTML) 65 Page - ATMEL Corporation |
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65 / 86 page  65 AT8xC5111 4190A–8051–11/02 Table 6. IPL1 Register IPL1 - Interrupt Priority Low Register 1 (S:B2H) Reset value = XXXX X00Xb Not Bit addressable. 765 43210 ---- - PSPI PADC - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2PSPI SPI Interrupt Priority level less significant bit. Refer to PSPIH for priority level. 1PADC ADC Interrupt Priority level less significant bit. Refer to PADCH for priority level. 0- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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