AT83C5111 datasheet(25/86 Pages) ATMEL

25 / 86 page

AT8xC5111

4190A–8051–11/02

Serial I/O Ports

Enhancements

The serial I/O ports in the AT8xC5111 are compatible with the serial I/O port in the

80C52.

They provide both synchronous and asynchronous communication modes. They oper-

ate as Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex

modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-

taneously and at different baud rates.

Serial I/O ports include the following enhancements:

•

Framing error detection

•

Automatic address recognition

Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2

and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-

ter (see Figure 7).

Figure 1. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register (see Table 25) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a reset can clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the

last data bit (see Figure 8 and Figure 9).

Figure 2. UART Timings in Mode 1

SM0 to UART mode control (SMOD0 = 0 for UART)

RB8

TB8

REN

SM2

SM1

IDL

GF0

GF1

POF

SMOD0

SMOD1

To UART framing error control

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1 for UART)

SCON for UART (98h) (SCON_1 for UART_1 (C0h))

PCON for UART (87h) (SMOD bits for UART_1

are located in BDRCON_1)

SM0/FE

Data Byte

SMOD0 = X

Stop

Bit

Start

Bit

RXD

SMOD0 = 1

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