AT83C5111 datasheet(7/86 Pages) ATMEL

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AT8xC5111

4190A–8051–11/02

Clock System

The AT8xC5111 oscillator system provides a reliable clocking system with full mastering

of speed versus CPU power trade off. Several clock sources are possible:

•

External clock input

•

High-speed crystal or ceramic oscillator

•

Integrated high-speed RC oscillator

The selected clock source can be divided by 2 - 512 before clocking the CPU and the

peripherals. When X2 function is set, the CPU needs 6 clock periods per cycle.

Clocking is controlled by several SFR registers: OSCON, CKCON0, CKCON1, CKRL.

Blocks Description

The AT8xC5111 includes the following oscillators:

•

Crystal oscillator

•

Integrated high-speed RC oscillator, with typical frequency of 12 MHz

Crystal Oscillator: OSCA

The crystal oscillator uses two external pins, XTAL1 for input and XTAL2 for output.

Both crystal and ceramic resonators can be used. An oscillator source on XTAL1 is

mandatory to start the product.

OSCAEN in OSCCON register is an enable signal for the crystal oscillator or the exter-

nal oscillator input.

Integrated High-speed RC

Oscillator: OSCB

The high-speed RC oscillator typical frequency is 12 MHz. Note that the on chip oscilla-

tor has a ±50% frequency tolerance and may not be suitable for use in some

applications.

OSCBEN in OSCCON register is an enable signal for the high-speed RC oscillator.

Clock Selector

CKS bit in CKS register is used to select from crystal to RC oscillator.

OSCBEN bit in OSCCON register is used to enable the RC oscillator.

OSCAEN bit in OSCCON register is used to enable the crystal oscillator or the external

oscillator input.

Clock Prescaler

Before supplying the CPU and the peripherals, the main clock is divided by a factor of 2

to 512, as defined by the CKRL register. The CPU needs from 12 to 256*12 clock peri-

ods per instruction. This allows:

•

to accept any cyclic ratio to be accepted on XTAL1 input.

•

to reduce the CPU power consumption.

The X2 bit allows to bypass the clock prescaler; in this case, the CPU needs only 6 clock

periods per machine cycle. In X2 mode, as this divider is bypassed, the signals on

XTAL1 must have a cyclic ratio between 40 to 60%.

AT83C5111 数据表(PDF) 7 Page - ATMEL Corporation

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