AT83C5111 datasheet(16/86 Pages) ATMEL

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AT8xC5111

4190A–8051–11/02

Hardware Watchdog

Timer (WDT)

The WDT is intended as a recovery method in situations where the CPU may be sub-

jected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer

Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable

the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca-

tion 0A6H. When WDT is enabled, it will increment every machine cycle (6 internal clock

periods) and there is no way to disable the WDT except through reset (either hardware

reset or WDT overflow reset). The T0 bit of the WDTPRG register is used to select the

overflow after 10 or 14 bits. When WDT overflows, it will generate an internal reset. It

will also drive an output RESET HIGH pulse at the emulator RST-pin. The length of the

reset pulse is 24 clock periods of the WD clock.

Using the WDT

To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST,

SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to

01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when

it reaches 16383 (3FFFH) or 1024 (1FFFH) and this will reset the device. When WDT is

enabled, it will increment every machine cycle while the oscillator is running. This means

the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the

user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The

WDT counter cannot be read or written. When WDT overflows, it will generate an output

RESET pulse at the RST pin. The RESET pulse duration is 96 x T

OSC, where TOSC =

1/F

OSC . To make the best use of the WDT, it should be serviced in those sections of

code that will periodically be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 27 counter has been added to extend the Time-out

capability, ranking from 16 ms to 2s at F

OSC = 12 MHz and T0 = 0. To manage this fea-

ture, refer to WDTPRG register description, Table 11 (SFR0A7h).

Table 1. WDTRST Register

WDTRST Address (0A6h)

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in

sequence.

Reset value

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