AT83C5111 datasheet(61/86 Pages) ATMEL

61 / 86 page

AT8xC5111

4190A–8051–11/02

Table 1. Priority Bit Level Values

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of higher priority level is serviced. If interrupt requests of the same priority level

are received simultaneously, an internal polling sequence determines which request is

serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

Table 2. Address Vectors

IPH.x

IP.x

Interrupt Level Priority

0 (Lowest)

011

102

3 (Highest)

Interrupt Name

Interrupt Address Vector

Priority Number

External Interrupt (INT0)

0003h

Timer0 (TF0)

000Bh

External Interrupt (INT1)

0013h

Timer1 (TF1)

001Bh

PCA (CF or CCFn)

0033h

UART (RI or TI)

0023h

SPI

004Bh

ADC

0043h

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