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AT83C5111 数据表(PDF) 75 Page - ATMEL Corporation |
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AT83C5111 数据表(HTML) 75 Page - ATMEL Corporation |
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75 / 86 page ![]() 75 AT8xC5111 4190A–8051–11/02 Figure 3. I CC Test Condition, Idle Mode Figure 4. I CC Test Condition, Power-Down Mode Figure 5. Clock Signal Waveform for I CC Tests in Active and Idle Modes RST XTAL2 XTAL1 V SS V CC I CC V CC Reset = V SS after a high pulse during at least 24 clock cycles V CC All other pins are disconnected. RST XTAL2 XTAL1 V SS V CC I CC (NC) V CC All other pins are disconnected. CLOCK SIGNAL Reset = VSS after a high pulse during at least 24 clock cycles V CC V CC-0.5V 0.45V 0.7V CC 0.2VCC-0.1 T CLCH T CHCL T CLCH = TCHCL = 5ns. |
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