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AT83C5111 数据表(PDF) 56 Page - ATMEL Corporation

部件名 AT83C5111
功能描述  Low Pin Count 8-bit Microcontroller with A/D Converter
PDF  86 Pages
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制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

AT83C5111 数据表(HTML) 56 Page - ATMEL Corporation

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AT8xC5111
4190A–8051–11/02
ADC Operation
Before starting a conversion, the A/D converter must be enabled, by setting the ADEN
bit, for at least T
setup (four microseconds).
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
From the ADSST set, the first full CONV_CK period will be the sampling period for the
ADC; during this period, the switch is closed and the capacitor is being charged. At the
end of the first period, the switch opens and the capacitor is no longer being charged.
During the next 10 CONV_CK periods, the sample and hold will be in hold mode during
the conversion. The busy flag ADSST(ADCON.3) remains set as long as an A/D conver-
sion is running. After completion of the A/D conversion, it is cleared by hardware. When
a conversion is running, this flag can be read only, a write has no effect.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is
available in ADDH and ADDL, it is cleared by software. If the bit EADC (IE1.1) is set, an
interrupt occur when flag ADEOC is set (see Figure 28). Clear this flag for re-arming the
interrupt.
From this point, if you keep starting a new conversion by resetting ADSST without
changing ADEN, it is not necessary to wait T
setup.
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.
Before starting normal power reduction modes the ADC conversion has to be com-
pleted.
Table 1. Selected Analog Input
Voltage Conversion
When the ADCIN is equal to VAREF, the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note that ADCIN should not exceed VAREF absolute maximum range.
SCH2
SCH1
SCH0
Selected Analog Input
00
0
AN0
00
1
AN1
01
0
AN2
01
1
AN3
10
0
AN4
10
1
AN5
11
0
AN6
11
1
AN7



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