AT83C5111 datasheet(60/86 Pages) ATMEL

60 / 86 page

AT8xC5111

4190A–8051–11/02

Interrupt System

The AT8xC5111 has a total of 8 interrupt vectors: two external interrupts (INT0 and

INT1), two timer interrupts (timers 0, 1), serial port interrupt, PCA, SPI and A/D. These

interrupts are shown in Figure 29.

Figure 1. Interrupt Control System

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register (See Table 49). This register also contains a

global disable bit, which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one of four priority levels

by setting or clearing a bit in the Interrupt Priority register (See Table 51) and in the

Interrupt Priority High register (see Table 53). Table 47 shows the bit values and priority

levels associated with each combination.

IE1

High Priority

Interrupt

Polling

Sequence

Low Priority

Interrupt

Global

Disable

Individual

Enable

TF0

INT0

INT1

TF1

IPH, IP

IE0

SPI

ADC

CCFx

PCA

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