DS31256 datasheet(109/183 Pages) MAXIM

109 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

109 of 183

Figure 9-11. Transmit DMA Memory Organization

Free Data Buffer Space

Transmit Pending-Queue Descriptors:

Contains Index Pointers to Packet

Descriptors of Queued Data Buffers that

are Ready to be Transmitted

Up to 64k dwords

Free-Queue Descriptors Allowed

Pending-Queue Base Address (32)

Pending-Queue End Address (16)

Pending-Queue Host Write Pointer (16)

Pending-Queue DMA Read Pointer (16)

Done-Queue Base Address (32)

Done-Queue End Address (16)

Done-Queue DMA Write Pointer (16)

Done-Queue Host Read Pointer (16)

Descriptor Base Address (32)

Used Data Buffer Space

Main Offboard Memory

(32-Bit Address Space)

Internal Registers

Transmit Done-Queue Descriptors:

Contains Index Pointers to Packet

Descriptors of Data Buffers that have

been Transmitted

Up to 64k dwords

Done-Queue Descriptors Allowed

Transmit Packet Descriptors:

Contains 32-Bit Addresses to Data

Buffers as well as Status/Control

Information and Links to Other Packet

Descriptors

Up to 64k quad dwords

Descriptors Allowed

DS31256 数据表(PDF) 109 Page - Maxim Integrated Products

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