 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
DS31256 数据表(PDF) 135 Page - Maxim Integrated Products |
|
|
|||||||||||||||||||||||||||||
DS31256 数据表(HTML) 135 Page - Maxim Integrated Products |
|
|
135 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 135 of 183 10.1.7 PCI Target Abort Targets can also abort the current transaction, which means they do not wish for the initiator to attempt the request again. No data is transferred in a target abort scenario. A target abort is signaled to the initiator by the simultaneous assertion of PSTOP and deassertion of PDEVSEL (Figure 10-8). When the DS31256 is a target, it only issues a target abort when the host is accessing the local bus. This occurs when the host attempts a bus transaction with a combination of byte enables ( PCBE) that are not supported by the local bus. If such a scenario occurs, it reports through the target-abort-initiated status bit in the PCI command/status configuration register (Section 10.2). See Section 11.1 for details about local bus operation. When the DS31256 is a bus master, if it detects a target abort, it reports through the target abort detected by master status bit in the PCI command/status configuration register (Section 10.2). Figure 10-8. PCI Target Abort 1 234 567 8910 PCLK PFRAME PSTOP PDEVSEL PTRDY |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
