ADAS1000-4BSTZ datasheet(28/80 Pages) AD

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ADAS1000-3/ADAS1000-4

Data Sheet

Rev. B | Page 28 of 80

ECG CHANNEL

The ECG channel consists of a programmable gain, low noise,

differential preamplifier; a fixed gain anti-aliasing filter; buffers;

and an ADC (see Figure 54). Each electrode input is routed to

its PGA noninverting input. Internal switches allow the PGA’s

inverting inputs to be connected to other electrodes and/or

the Wilson Central Terminal to provide differential analog

processing (analog lead mode), to a computed average of some

or all electrodes, or to the internal 1.3 V common-mode

reference (VCM_REF). The latter two modes support digital

lead mode (leads computed on-chip) and electrode mode (leads

calculated off-chip). In all cases, the internal reference level is

removed from the final lead data.

The ADAS1000-3/ADAS1000-4 implementation uses a dc-

coupled approach, which requires that the front end be biased

to operate within the limited dynamic range imposed by the

relatively low supply voltage. The right leg drive loop performs

this function by forcing the electrical average of all selected

electrodes to the internal 1.3 V level, VCM_REF, maximizing

each channel’s available signal range.

All ECG channel amplifiers use chopping to minimize 1/f noise

contributions in the ECG band. The chopping frequency of

~250 kHz is well above the bandwidth of any signals of interest.

The 2-pole anti-aliasing filter has ~65 kHz bandwidth to support

digital pace detection while still providing greater than 80 dB

of attenuation at the ADC’s sample rate. The ADC is a 14-bit,

2 MHz SAR converter; 1024 × oversampling helps achieve the

required system performance. The ADC’s full-scale input range

is 2 × VREF, or 3.6 V, although the analog portion of the ECG

channel limits the useful signal swing to about 2.8 V. The

ADAS1000 contains flags to indicate whether the ADC data is

out of range, indicating a hard electrode off state. Programmable

overrange and underrange thresholds are shown in the LOFFUTH

and LOFFLTH registers (see Table 39 and Table 40, respectively).

The ADC out of range flag is contained in the header word (see

Table 53).

Figure 54. Simplified Schematic of a Single ECG Channel

ADC

TO COMMON-MODE AMPLIFIER

FOR DRIVEN LEG AND

SHIELD DRIVER

AVDD

VREF

ELECTRODE

PREAMP

G = 1, 1.5, 2, 3

FILTER

DIFF AMP

BUFFER

G = 1.4

PATIENT

CABLE

EXTERNAL

RFI AND DEFIB

PROTECTION

VCM

–

ELECTRODE

EXTERNAL

RFI AND DEFIB

PROTECTION

ADAS1000-3/

ADAS1000-4

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