ADAS1000-4BSTZ datasheet(36/80 Pages) AD

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ADAS1000-3/ADAS1000-4

Data Sheet

CALIBRATION DAC

Within the ADAS1000-3/ADAS1000-4, there are a number of

calibration features.

The 10-bit calibration DAC can be used to correct channel gain

errors (to ensure channel matching) or to provide several test

tones. The options are as follows:

•

DC voltage output (range: 0.3 V to 2.7 V). The DAC

transfer function for dc voltage output is

(

)













−

code

•

1 mV p-p sine wave of 10 Hz or 150 Hz

•

1 mV 1 Hz square wave

Internal switching allows the calibration DAC signals to be

routed to the input of each ECG channel (see Figure 63).

Alternatively, it can be driven out from the CAL_DAC_IO

pin, enabling measurement and correction for external error

sources in the entire ECG signal chain.

To ensure a successful update of the calibration DAC (see

Table 36), the host controller must issue four additional SCLK

cycles after writing the new calibration DAC register word.

GAIN CALIBRATION

The gain for each ECG channel can be adjusted to correct

for gain mismatches between channels. Factory trimmed

gain correction coefficients are stored in nonvolatile memory

on-chip for GAIN 0, GAIN 1, and GAIN 2; there is no factory

calibration for GAIN 3. The default gain values can be over-

written by user gain correction coefficients, which are stored

in volatile memory and available by addressing the appropriate

gain control registers (see Table 50). The gain calibration applies

to the ECG data available on the standard interface and applies

to all data rates.

LEAD-OFF DETECTION

An ECG system must be able to detect if an electrode is no

longer connected to the patient. The ADAS1000-3/ADAS1000-4

support two methods of lead-off detection, ac lead-off detection

and dc lead-off detection. The two systems are independent and

can be used singly or together under the control of the serial

interface (see Table 29).

A lead-off event sets a flag in the frame header word (see Table 53).

Identification of which electrode is off is available as part of the

data frame or as a register read from the lead-off status register

(Register LOFF, see Table 47). In the case of ac lead-off, infor-

mation about the amplitude of the lead-off signal or signals can

be read back through the serial interface (see Table 51).

In a typical ECG configuration, the electrodes RA, LA, and LL

are used to generate a common mode of Wilson Central Terminal

(WCT). If one of these electrodes is off, this affects the WCT

signal and any lead measurements that it contributes to. As a

result, the ECG measurements on these signals are expected to

degrade. The user has full control over the common-mode

amplifier and can adjust the common-mode configuration to

remove that electrode from the common-mode generation. In

this way, the user can continue to make measurements on the

remaining connected leads.

DC Lead-Off Detection

This method injects a small programmable dc current into each

input electrode. When an electrode is properly connected, the

current flows into the right leg (RLD_OUT) and produces a

minimal voltage shift. If an electrode is off, the current charges

that pin’s capacitance, causing the voltage at the pin to float

positive and create a large voltage change that is detected by

the comparators in each channel. These comparators use fixed,

gain-independent upper and lower threshold voltages of 2.4 V

and 0.2 V, respectively. If the input exceeds either of these levels,

the lead-off flag is raised. The lower threshold is included in the

event that something pulls the electrode down to ground.

The dc lead-off detection current can be programmed via the

serial interface. Typical currents range from 10 nA to 70 nA in

10 nA steps. All input pins (RA, LA, LL, V1, V2, and CM_IN)

use identical dc lead-off detection circuitry.

Detecting if the right-leg electrode has fallen off is necessarily

different as RLD_OUT is a low impedance amplifier output. A

pair of fixed threshold comparators monitor the output voltage

to detect amplifier saturation that would indicate a lead-off

condition. This information is available in the DCLEAD-OFF

input pins.

The propagation delay for detecting a dc lead-off event depends

on the cable capacitance and the programmed current. It is

approximately

Delay = Voltage × Cable Capacitance/Programmed Current

For example:

Delay = 1.2 V × (200 pF/70 nA) = 3.43 ms

DC Lead-Off and High Gains

Using dc lead-off at high gains can result in failure of the circuit

to flag a lead-off condition. The chopping nature of the input

amplifier stage contributes to this situation. When the electrode

is off, the electrode is pulled up; however, in this gain setting,

the first stage amplifier goes into saturation before the input

signal crosses the DCLO upper threshold, resulting in no lead-

off flag. This affects the gain setting GAIN 3 (4.2) and partially

GAIN 2 (2.8).

Increasing the AVDD voltage raises the voltage at which the input

amplifiers saturate, allowing the off electrode voltage to rise high

enough to trip the DCLO comparator (fixed upper threshold of

2.4 V). The ADAS1000 operates over a voltage range of 3.15 V

to 5.5 V. If using GAIN 2/GAIN 3 and dc lead-off, an increased

AVDD supply voltage (minimum 3.6 V) allows dc lead-off to

flag correctly at higher gains.

Rev. B | Page 36 of 80

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