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ADAS1000-4BSTZ 数据表(PDF) 13 Page - Analog Devices |
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ADAS1000-4BSTZ 数据表(HTML) 13 Page - Analog Devices |
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13 / 80 page  Data Sheet ADAS1000-3/ADAS1000-4 Rev. B | Page 13 of 80 Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000-4 Only AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. The following timing specifications apply for the master interface when the ECGCTL register is configured for high performance mode (ECGCTL[3] = 1), see Table 28. Table 6. Parameter1 Min Typ Max Unit Description Output Frame Rate2 128 kHz All five 16-bit ECG data-words are available at frame rate of 128 kHz only fSCLK2 2.5 × crystal frequency MHz Crystal frequency = 8.192 MHz tMCSSA 24.4 ns A MCSE A valid setup time tMDO 0 ns MSCLK rising edge to MSDO valid delay tMCSHD 48.8 ns A MCSE A valid hold time from MSCLK falling edge tMCSW 2173 ns A MCSE A high time, SPIFW = 0, A MCSE A asserted for entire frame as shown in Figure 5, and configured in Table 33 2026 ns A MCSE A high time, SPIFW = 1, A MCSE A asserted for each word in frame as shown in Figure 6 and configured in Table 33 1 Guaranteed by characterization, not production tested. 2 Guaranteed by design, not production tested. Figure 5. Data Read and Write Timing Diagram for SPIFW = 0, Showing Entire Packet Of Data (Header, 5 ECG Word = [ECG1, ECG2, ECG3 and 2 Words with Zeros], and CRC Word) Figure 6. Data Read and Write Timing Diagram for SPIFW = 1, Showing Entire Packet Of Data (Header, 5 ECG Word = [ECG1, ECG2, ECG3 and 2 Words with Zeros], and CRC Word) tMSCLK tMCSSA tMSCLK 2 MSCLK MCS tMCSHD MSDO D0_15 tMDO MSB D0_14 D0_1 D1_15 LSB SPIFW = 0* D5_0 D0_0 D1_14 *SPIFW = 0 PROVIDES MCS FOR EACH FRAME, SCLK STAYS HIGH FOR 1/2 MSCLK CYCLE BETWEEN EACH WORD. D6_15 MSB D6_14 MSB LSB D6_0 LSB HEADER: 0xF AND 12-BIT COUNTER 5 × 16-BIT ECG DATA 16-BIT CRC WORD tMCSW tMSCLK tMCSSA tMCSHD MSCLK MCS MSDO SPIFW = 1* tMSCLK tMCSW D0_15 t MDO MSB D0_14 D0_1 D1_15 LSB D5_0 D0_0 D1_14 D6_15 MSB D6_14 MSB LSB D6_0 LSB 5 × 16-BIT ECG DATA HEADER: 0xF AND 12-BIT COUNTER 16-BIT CRC WORD *SPIFW = 1 PROVIDES MCS FOR EACH FRAME, SCLK STAYS HIGH FOR 1 MSCLK CYCLE BETWEEN EACH WORD. |
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