ADAS1000-4BSTZ datasheet(16/80 Pages) AD

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ADAS1000-3/ADAS1000-4

Data Sheet

Rev. B | Page 16 of 80

Table 9. Pin Function Descriptions

ADAS1000-3 Pin No.

ADAS1000-4 Pin No.

Mnemonic

Description

LQFP

LFCSP

LQFP

LFCSP

18, 23,

58, 63

15, 20,

51, 56

18, 23, 58,

15, 20, 51,

AVDD

Analog Supply. See recommendations for bypass capacitors in the Power Supply,

Grounding, and Decoupling Strategy section.

35, 46

30, 41

35, 46

30, 41

IOVDD

Digital Supply for Digital Input/Output Voltage Levels. See recommendations for

bypass capacitors in the Power Supply, Grounding, and Decoupling Strategy section.

26, 55

23, 48

26, 55

23, 48

ADCVDD

Analog Supply for ADC. There is an on-chip linear regulator providing the supply

voltage for the ADCs. These pins are primarily provided for decoupling purposes;

however, the pin may also be supplied by an external 1.8 V supply should the user wish

to use a more efficient supply to minimize power dissipation. In this case, use the

VREG_EN pin tied to ground to disable the ADCVDD and DVDD regulators. The

ADCVDD pin should not be used to supply other functions. See recommendations for

bypass capacitors in the Power Supply, Grounding, and Decoupling Strategy section.

30, 51

27, 44

30, 51

27, 44

DVDD

Digital Supply. There is an on-chip linear regulator providing the supply voltage for the

digital core. These pins are primarily provided for decoupling purposes; however, the

pin may also be overdriven supplied by an external 1.8 V supply should the user wish to

use a more efficient supply to minimize power dissipation. In this case, use the

VREG_EN pin tied to ground to disable the ADCVDD and DVDD regulators. See

recommendations for bypass capacitors in the Power Supply, Grounding, and

Decoupling Strategy section.

2, 15, 24,

25, 56, 57

1, 14, 21,

22, 49, 50

2, 15, 24,

25, 56, 57

1, 14, 21,

22, 49, 50

AGND

Analog Ground.

31, 34,

40, 47, 50

28, 29,

36, 42, 43

31, 34, 40,

47, 50

28, 29, 36,

42, 43

DGND

Digital Ground.

VREG_EN

Enables or disables the internal voltage regulators used for ADCVDD and DVDD. Tie this

pin to AVDD to enable or tie this pin to ground to disable the internal voltage

regulators.

ECG1_LA

Analog Input, Left Arm (LA).

ECG2_LL

Analog Input, Left Leg (LL).

ECG3_RA

Analog Input, Right Arm (RA).

EXT_RESP_RA

Optional External Respiration Input.

EXT_RESP_LL

Optional External Respiration Input.

EXT_RESP_LA

Optional External Respiration Input.

RESPDAC_LL

Optional Path for Higher Performance Respiration Resolution, Respiration DAC Drive,

Negative Side 0.

SHIELD/

RESPDAC_LA

Shared Pin (User-Configured).

Output of Shield Driver (SHIELD).

Optional Path for Higher Performance Respiration Resolution, Respiration DAC Drive,

Negative Side 1 (RESPDAC_LA).

SHIELD

Output of Shield Driver.

RESPDAC_RA

Optional Path for Higher Performance Respiration Resolution, Respiration DAC Drive,

Positive Side.

CM_OUT/WCT

Common-Mode Output Voltage (Average of Selected Electrodes). Not intended to drive

current.

CM_IN

Common-Mode Input.

RLD_SJ

Summing Junction for Right Leg Drive Amplifier.

RLD_OUT

Output and Feedback Junction for Right Leg Drive Amplifier.

CAL_DAC_IO

Calibration DAC Input/Output. Output for a master device, input for a slave. Not

intended to drive current.

REFIN

Reference Input. For standalone mode, use REFOUT connected to REFIN. External 10 μF

capacitors with ESR < 0.2 Ω in parallel with 0.1 μF bypass capacitors to GND are

required and should be placed as close to the pin as possible. An external reference can

be connected to REFIN.

REFOUT

Reference Output.

REFGND

Reference Ground. Connect to a clean ground.

27, 28

47, 46

27, 28

47, 46

XTAL1, XTAL2

External crystal connects between these two pins; external clock drive should be

applied to CLK_IO. Each XTAL pin requires a 15 pF capacitor to ground.

CLK_IO

Buffered Clock Input/Output. Output for a master device; input for a slave. Powers up in

high impedance.

CSE

Chip Select and Frame Sync, Active Low.

CSE

can be used to frame each word or to frame

the entire suite of data in framing mode.

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