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ADAS1000-4BSTZ 数据表(PDF) 11 Page - Analog Devices

部件名 ADAS1000-4BSTZ
功能描述  Low Power, Three Electrode Electrocardiogram (ECG) Analog Front End
PDF  80 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAS1000-4BSTZ 数据表(HTML) 11 Page - Analog Devices

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Data Sheet
ADAS1000-3/ADAS1000-4
Rev. B | Page 11 of 80
TIMING CHARACTERISTICS
Standard Serial Interface
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C.
Table 5.
IOVDD
Parameter1
3.3 V
2.5 V
1.8 V
Unit
Description
Output Rate2
2
128
kHz
Across specified IOVDD supply range; three programmable output data
rates available as configured in FRMCTL register (see Table 37) 2 kHz,
16 kHz, 128 kHz; use skip mode for slower rates.
SCLK Cycle Time
25
40
50
ns min
See Table 21 for details on SCLK frequency vs. packet data/frame rates.
tCSSA
8.5
9.5
12
ns min
A
CSE
A
valid setup time to rising SCLK.
tCSHA
3
3
3
ns min
A
CSE
A
valid hold time to rising SCLK.
tCH
8
8
8
ns min
SCLK high time.
tCL
8
8
8
ns min
SCLK low time.
tDO
8.5
11.5
20
ns typ
SCLK falling edge to SDO valid delay; SDO capacitance of 15 pF.
11
19
24
ns max
tDS
2
2
2
ns min
SDI valid setup time from SCLK rising edge.
tDH
2
2
2
ns min
SDI valid hold time from SCLK rising edge.
tCSSD
2
2
2
ns min
A
CSE
A
valid setup time from SCLK rising edge.
tCSHD
2
2
2
ns min
A
CSE
A
valid hold time from SCLK rising edge.
tCSW
25
40
50
ns min
A
CSE
A
high time between writes (if used). Note that
A
CSE
A
is an optional input,
it may be tied permanently low. See a full description in the Serial
Interfaces section.
tDRDY_CS2
0
0
0
ns min
A
DRDYE
A
to
A
CSE
A
setup time.
tCSO
6
7
9
ns typ
Delay from
A
CSE
A
assert to SDO active.
A
RESETE
A
Low Time2
20
20
20
ns min
Minimum pulse width;
A
RESETE
A
is edge triggered.
1 Guaranteed by characterization, not production tested.
2 Guaranteed by design, not production tested.
Figure 2. Data Read and Write Timing Diagram (CPHA = 1, CPOL = 1)
DB[30]
DB[31]
DB[0]
DB[1]
DB[29]
DB[25]
DB[24]
DB[23]
SCLK
CS
SDI
tCH
tCL
tCSSA
tCSHA
tCSHD
tCSSD
tDH
tDS
tCSW
SDO
tDO
R/W
MSB
LSB
DATA
ADDRESS
DO_25
DO_1
DO_0
DO_29
DO_30
DO_31
DRDY
MSB
LSB
tCSO



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