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ADAS1000-4BSTZ 数据表(PDF) 57 Page - Analog Devices |
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ADAS1000-4BSTZ 数据表(HTML) 57 Page - Analog Devices |
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57 / 80 page  Data Sheet ADAS1000-3/ADAS1000-4 13B SPI REGISTER DEFINITIONS AND MEMORY MAP In 2 kHz and 16 kHz data rates, data takes the form of 32-bit words. Bit A6 to Bit A0 serve as word identifiers. Each 32-bit word has 24 bits of data. A third high speed data rate is also offered: 128 kHz with data in the form of 16-bit words (all 16 bits as data). Table 26. SPI Register Memory Map AA REE AA /W121 A[6:0] D[23:0] Register Name Table Register Description Reset Value R 0x00 XXXXXX NOP NOP (no operation) 0x000000 R/W 0x01 dddddd ECGCTL Table 28 ECG control 0x000000 R/W 0x02 dddddd LOFFCTL Table 29 Lead-off control 0x000000 R/W 0x03 dddddd RESPCTL Table 30 Respiration control2 0x000000 R/W 0x04 dddddd PACECTL Table 31 Pace detection control 0x000F88 R/W 0x05 dddddd CMREFCTL Table 32 Common-mode, reference, and shield drive control 0xE00000 R/W 0x06 dddddd GPIOCTL Table 33 GPIO control 0x000000 R/W 0x07 dddddd PACEAMPTH Table 34 Pace amplitude threshold2 0x242424 R/W 0x08 dddddd TESTTONE Table 35 Test tone 0x000000 R/W 0x09 dddddd CALDAC Table 36 Calibration DAC 0x002000 R/W 0x0A dddddd FRMCTL Table 37 Frame control 0x079000 R/W 0x0B dddddd FILTCTL Table 38 Filter control 0x000000 R/W 0x0C dddddd LOFFUTH Table 39 AC lead-off upper threshold 0x00FFFF R/W 0x0D dddddd LOFFLTH Table 40 AC lead-off lower threshold 0x000000 R/W 0x0E dddddd PACEEDGETH Table 41 Pace edge threshold2 0x000000 R/W 0x0F dddddd PACELVLTH Table 42 Pace level threshold2 0x000000 R 0x11 XXXXXX LADATA Table 43 LA or Lead I data 0x000000 R 0x12 XXXXXX LLDATA Table 43 LL or Lead II data 0x000000 R 0x13 XXXXXX RADATA Table 43 RA or Lead III data 0x000000 R 0x1A XXXXXX PACEDATA Table 44 Read pace detection data/status2 0x000000 R 0x1B XXXXXX RESPMAG Table 45 Read respiration data—magnitude2 0x000000 R 0x1C XXXXXX RESPPH Table 46 Read respiration data—phase2 0x000000 R 0x1D XXXXXX LOFF Table 47 Lead-off status 0x000000 R 0x1E XXXXXX DCLEAD-OFF Table 48 DC lead-off 0x000000 R 0x1F XXXXXX OPSTAT Table 49 Operating state 0x000000 R/W 0x21 dddddd CALLA Table 50 User gain calibration LA 0x000000 R/W 0x22 dddddd CALLL Table 50 User gain calibration LL 0x000000 R/W 0x23 dddddd CALRA Table 50 User gain calibration RA 0x000000 R 0x31 dddddd LOAMLA Table 51 Lead-off amplitude for LA 0x000000 R 0x32 dddddd LOAMLL Table 51 Lead-off amplitude for LL 0x000000 R 0x33 dddddd LOAMRA Table 51 Lead-off amplitude for RA 0x000000 R 0x3A dddddd PACE1DATA Table 52 Pace1 width and amplitude2 0x000000 R 0x3B dddddd PACE2DATA Table 52 Pace2 width and amplitude2 0x000000 R 0x3C dddddd PACE3DATA Table 52 Pace3 width and amplitude2 0x000000 R 0x40 dddddd FRAMES Table 53 Frame header 0x800000 R 0x41 XXXXXX CRC Table 54 Frame CRC 0xFFFFFF x Other XXXXXX Reserved3 Reserved XXXXXX 1 R/W = register both readable and writable; R = read only. 2 ADAS1000-4 model only, ADAS1000-3 model does not contain these features. 3 Reserved bits in any register are undefined. In some cases, a physical (but unused) memory bit may be present—in other cases not. Do not issue commands to reserved registers/space. Read operations of unassigned bits are undefined . Rev. B | Page 57 of 80 |
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