ADAS1000-4BSTZ datasheet(58/80 Pages) AD

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ADAS1000-3/ADAS1000-4

Data Sheet

CONTROL REGISTERS DETAILS

For each register address, the default setting is noted in a default column in addition to being noted in the function column by “(default)”;

this format applies throughout the register map.

Table 27. Serial Bit Assignment

B31

[B30:B24]

[B23:B0]

Address bits

Data bits (MSB first)

Table 28. ECG Control Register (ECGCTL) Address 0x01, Reset Value = 0x000000

REE

Default

Bit

Name

Function

R/W

LAEN

ECG channel enable; shuts down power to the channel; the input becomes high-Z.

0 (default) = disables ECG channel. When disabled, the entire ECG channel is shut down and dissipates

minimal power.

1 = enables ECG channel.

R/W

LLEN

R/W

RAEN

[20:11]

Reserved

Reserved, set to 0.

R/W

CHCONFIG

Setting this bit selects the differential analog front-end (AFE) input. See

Figure 56.

0 (default) = single-ended input (digital lead mode or electrode mode).

1 = differential input (analog lead mode).

R/W

[9:8]

GAIN [1:0]

Preamplifier and anti-aliasing filter overall gain.

00 (default) = GAIN 0 = ×1.4.

01 = GAIN 1 = ×2.1.

10 = GAIN 2 = ×2.8.

11 = GAIN 3 = ×4.2 (user gain calibration is required for this gain setting).

R/W

VREFBUF

VREF buffer enable.

0 (default) = disabled.

1 = enabled (when using the internal VREF, VREFBUF must be enabled).

R/W

CLKEXT

Use external clock instead of crystal oscillator. The crystal oscillator is automatically disabled if

configured as a slave in gang mode and the slave device should receive the clock from the master

device.

0 (default) = XTAL is clock source.

1 = CLK_IO is clock source.

R/W

Master

In gang mode, this bit selects the master (SYNC_GANG pin is configured as an output). When in single

channel mode (gang = 0), this bit is ignored

0 (default) = slave.

1 = master.

R/W

Gang

Enable gang mode. Setting this bit causes CLK_IO and SYNC_GANG to be activated.

0 (default) = single channel mode.

1 = gang mode.

R/W

Selects the noise/power performance. This bit controls the ADC sampling frequency. See the

Specifications section for further details. This bit also affects the respiration carrier frequency as

discussed in the Respiration Carrier Frequency section.

0 (default) = 1 MSPS, low power.

1 = 2 MSPS, high performance/low noise.

R/W

CNVEN

Conversion enable. Setting this bit enables the ADC conversion and filters.

0 (default) = idle.

1 = conversion enable.

R/W

PWREN

Power enable. Clearing this bit powers down the device. All analog blocks are powered down and the

external crystal is disabled. The register contents are retained during power down as long as DVDD is

not removed.

0 (default) = power down.

1 = power enable.

R/W

SWRST

Software reset. Setting this bit clears all registers to their reset value. This bit automatically clears itself.

The software reset requires a NOP command to complete the reset.

0 (default) = NOP.

1 = reset.

Rev. B | Page 58 of 80

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