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ADAS1000-4BSTZ 数据表(PDF) 76 Page - Analog Devices |
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ADAS1000-4BSTZ 数据表(HTML) 76 Page - Analog Devices |
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76 / 80 page ![]() ADAS1000-3/ADAS1000-4 Data Sheet 100B Example 6: Writing to Master and Slave Devices and Streaming Conversion Data This example uses the ADAS1000-3 as the slave device and the ADAS1000 as the master device to achieve a configuration with eight input electrodes and one right leg drive. 101B101B Slave Configuration (ADAS1000-3) 1. Write 1 configures the FRMCTL register to output five words per frame/packet. The frame/packet of words consists of the header, three ECG words, and lead-off. The frame is configured to always send, irrespective of ready status. The slave ADAS1000-3 is in electrode mode format with a data rate of 2 kHz. 2. Write 2 configures the CMREFCTL register to receive an external common mode from the master. 3. Write 3 addresses the ECGCTL register, enabling all channels into a gain of 1.4, low noise mode. It configures the device as a slave, in gang mode and driven from the CLK_IN input source (derived from master ADAS1000). The ADAS1000-3 slave is also put into conversion mode in this write, but waits for the SYNC_GANG signal from the master device before it starts converting. 102B102B Master Configuration (ADAS1000) • Write 4 configures the FRMCTL register to output seven words per frame/packet (note that this differs from the number of words in a frame available from the slave device). The frame/packet of words consists of the header, five ECG words, pace, respiration magnitude, and lead-off. In this example, the frame is configured to always send irrespective of ready status. The master, ADAS1000, is in vector mode format with a data rate of 2 kHz. Similar to the slave device, the master could be configured for electrode mode; the host controller would then be required to make the lead calculations. 1. Write 5 configures the CMREFCTL register for CM = WCT = (LA + LL + RA)/3; RLD is enabled onto RLD_OUT electrode. The shield amplifier is enabled. The CM = WCT signal is driven out of the master device (CM_OUT) into the slave device (CM_IN). 2. Write 6 addresses the ECGCTL register, enabling all channels into a gain of 1.4, low noise mode. It configures the device as a master in gang mode and driven from the XTAL input source. The ADAS1000 master is set to differential input, which places it in analog lead mode. This ECGCTL register write puts the master into conversion mode, where the device sends an edge on the SYNC_GANG pin to the slave device to trigger the simultaneous conversions of both devices. 3. Write 7 issues the read command to both devices to start putting the converted and decimated data out on the respective SDO pins. 4. Continue to issue SCLK cycles to read the converted data at the configured packet data rate. Table 60. Example 6: Writing to Master and Slave Devices and Streaming Conversion Data Device Write Command Register Addressed R/W Register Address Data 32-Bit Write Command Slave Write 1 FRMCTL 1 000 1010 0001 1111 1111 0110 0001 0000 0x8A1FF610 Write 2 CMREFCTL 1 000 0101 0000 0000 0000 0000 0000 0100 0x85000004 Write 3 ECGCTL 1 000 0001 1110 0000 0000 0000 1101 1110 0x81E000DE Master Write 4 FRMCTL 1 000 1010 0001 1111 1001 0110 0000 0000 0x8A1F9600 Write 5 CMREFCTL 1 000 0101 1110 0000 0000 0000 0000 1011 0x85E0000B Write 6 ECGCTL 1 000 0001 1110 0000 0000 0100 1011 1110 0x81E004BE Master and Slave Write 7 FRAMES 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000 Rev. B | Page 76 of 80 |
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