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Data Sheet

ADAS1000-3/ADAS1000-4

48B

SECONDARY SERIAL INTERFACE

This second serial interface is an optional interface that

can be used for the user’s own pace detection purposes.

This interface contains ECG data at 128 kHz data rate only.

If using this interface, the ECG data is still available on the

standard interface discussed previously at lower rates with all

the decimation and filtering applied. If this interface is inactive,

it draws no power.

Data is available in 16-bit words, MSB first.

This interface is a master interface, with the ADAS1000-3/

ADAS1000-4 providing the SCLK,

CSEE

, SDO. Is it shared

across some of the existing GPIO pins as follows:

•

GPIO1/MSCLK

•

GPIO0/

MCSEE

•

GPIO2/MSDO

This interface can be enabled via the GPIO register (see

Table 33).

Figure 78. Master SPI Interface for External Pace Detection Purposes

The data format of the frame starts with a header word, three

ECG data-words, two words filled with zeros and completes

with the same CRC word as documented in Table 24 for the

128 kHz rate. All words are 16 bits. MSCLK runs at approxi-

mately 20 MHz and the

MCSEE

function is asserted for the entire

frame with the data available on MSDO on the falling edge of

MSCLK. MSCLK idles high when

MCSEE

is deasserted.

The data format for this interface is fixed and not influenced by

the FRMCTL register settings. All six words are output, even if

the individual channels are not enabled.

The header word consists of four bits of all 1s followed by a 12-

bit sequence counter. This sequence counter increments after

every frame is sent, thereby allowing the user to tell if any

frames have been missed and how many.

RESETEE

There are two methods of resetting the ADAS1000-3/ADAS1000-4

to power-on default. Bringing the

RESETEE

line low or setting

the SWRST bit in the ECGCTL register (Table 28) resets the

contents of all internal registers to their power-on reset state.

The falling edge of the

RESETEE

pin initiates the reset

process;

DRDYEE

goes high for the duration, returning low when

the

RESETEE

process is complete. This sequence takes 1.5 ms

maximum. Do not write to the serial interface while

DRDYEE

high handling a

RESETEE

command. When

DRDYEE

returns low,

normal operation resumes and the status of the

RESETEE

pin is

ignored until it goes low again. Software reset using the SWRST

bit (see Table 28) requires that a NOP (no operation) command

be issued to complete the reset cycle.

PDEE

FUNCTION

The

PDEE

pin powers down all functions in low power mode.

The digital registers maintain their contents. The power-down

function is also available via the serial interface (ECG control

Table 25. Master SPI Frame Format; All Words are 16 Bits

Mode\Word

Electrode mode1

Header

ECG1_LA

ECG2_LL

ECG3_RA

All 0’s

CRC

Analog lead mode1

Header

LEAD I

LEAD III

−LEAD II (RA-LL)

All 0’s

CRC

As set by the FRMCTL register data DATAFMT, Bit [4], see Table 37.

ADAS1000-4

MASTER SPI

SCLK

MCS/GPIO0

MICROCONTROLLER/

DSP

MSDO/GPIO2

MISO/GPIO

MSCLK/GPIO1

Rev. B | Page 55 of 80

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