| 数据搜索系统,热门电子元器件搜索 |
|
AR8327-AL1A-R 数据表(PDF) 267 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
AR8327-AL1A-R 数据表(HTML) 267 Page - List of Unclassifed Manufacturers |
|
267 / 394 page ![]() Atheros Communications, Inc. AR8327/AR8327N Seven-port Gigabit Ethernet Switch • 267 3.7.94 ACL_RATE_CTRL1_5 Address 0x0A28 SFT&HW RST Table 3-245, “ACL_5 Rate Control Register,” on page 267 summerizes the ACL_RATE_CTRL1_5 Register 1 Table 3-245. ACL_5 Rate Control Register 3.7.95 ACL_RATE_CTRL1_5 Address 0x0A2C SFT&HW RST Table 3-246, “ACL_5 Rate Control Register 1,” on page 267 summerizes the ACL_RATE_CTRL1_5 Register 1 Table 3-246. ACL_5 Rate Control Register 1 17:15 R/W 0 ACL_EBS_4 Excess burst size for ingress rate limit 14:0 R/W 0x7FFF ACL_EIR_4 Ingress Rate Limit for all priority. Rate is limited to times of 32kbps. Default 15'h7FFF is for disable rate limit for ingress. if these bits are set to 15'h0, no frame should be received in from this port. Bit R/W Inital Value Mnemonic Description Bit R/W Inital Value Mnemonic Description 31:18 R/O 0 RESERVED 17:15 R/W 0 ACL_CBS_5 Commited burst size for ingress rate limit 14:0 R/W 0x7FFF ACL_CIR_5 Ingress Rate Limit for all priority. Rate is limited to times of 32kbps. Default 15'h7FFF is for disable rate limit for ingress. if these bits are set to 15'h0, no frame should be received in from this port. Bit R/W Inital Value Mnemonic Description 31:24 R/O 0 RESERVED 23 R/W 0 ACL_BORROW_EN_5 Borrow enable |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |