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EDB8164B4PR-1DITF-R 数据表(PDF) 145 Page - Micron Technology

部件名 EDB8164B4PR-1DITF-R
功能描述  216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Features
PDF  152 Pages
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

EDB8164B4PR-1DITF-R 数据表(HTML) 145 Page - Micron Technology

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Data Setup, Hold, and Slew Rate Derating
For all input signals (DQ, DM) the total required setup time (tDS) and hold time (tDH)
are calculated by adding the data sheet tDS(base) and tDH(base) values (see the follow-
ing table) to the ΔtDS and ΔtDH derating values, respectively (see the following derating
tables). Example: tDS = tDS(base) + ΔtDS.
The typical tDS slew rate for a rising signal is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC)min. The typical tDS slew rate for a
falling signal is defined as the slew rate between the last crossing of VREF(DC) and the
first crossing of VIL(AC)max (see the Typical Slew Rate and tVAC – tDS for DQ Relative to
Strobe figure).
If the actual signal is consistently earlier than the typical slew rate line in the figure,
"Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock (CA and CS_n Setup,
Hold, and Derating), the area shaded gray between the VREF(DC) region and the AC re-
gion, use the typical slew rate for the derating value. If the actual signal is later than the
typical slew rate line anywhere between the shaded VREF(DC) region and the AC region,
the slew rate of a tangent line to the actual signal from the AC level to the DC level is
used for the derating value (see figure "Tangent Line – tIS for CA and CS_n Relative to
Clock" in CA and CS_n Setup, Hold, and Derating).
The typical tDH slew rate for a rising signal is defined as the slew rate between the last
crossing of VIL(DC)max and the first crossing of VREF(DC). The typical tDH slew rate for a
falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the
first crossing of VREF(DC) (see the Typical Slew Rate – DH for DQ Relative to Strobe fig-
ure).
If the actual signal is consistently later than the typical slew rate line between the
shaded DC-level-to-VREF(DC) region, the typical slew rate should be used for the derating
value. If the actual signal is earlier than the typical slew rate line anywhere between sha-
ded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the
DC level to the VREF(DC) level is used for the derating value (see the Tangent Line – tDH
for DQ with Respect to Strobe figure).
For a valid transition, the input signal must remain above or below VIH/VIL(AC) for the
specified time, tVAC (see the Required Time for Valid Transition – tVAC > VIH(AC) or <
VIL(AC) table).
The total setup time for slow slew rates could be negative; that is, a valid input signal
may not have reached VIH/VIL(AC) at the time of the rising clock transition. A valid input
signal is still required to complete the transition and reach VIH/VIL(AC).
For slew rates between the values listed in the following tables, the derating values can
be obtained using linear interpolation. Typically, slew rate values are not subject to pro-
duction testing. They are verified by design and characterization.
Table 97: Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate)
Parameter
Data Rate
Reference
1066
933
800
667
533
466
tDS (base)
-10
15
50
130
210
230
VIH/VIL(AC) = VREF(DC) ±220mV
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Data Setup, Hold, and Slew Rate Derating
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
145
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.



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