MPFS250T datasheet(113/128 Pages) MICROCHIP

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Table 141 • System Controller Suspend Entry and Exit Characteristics

Unit

Max

Typ

Definition

Symbol

Parameter

Suspend entry time

from TRST_N asser-

tion

Tsuspend_Tr

1, 2

Time from TRSTb

falling edge to SUS-

PEND_EN signal as-

sertion

372

361

Suspend exit time

from TRST_N nega-

tion

Tsuspend_exit

Time from TRSTb

rising edge to ACTI-

VE signal assertion

1. ACTIVE indicates that the system controller is inactive or active regardless of the state of SUSPEND_EN.

2. ACTIVE signal must never be asserted with SUSPEND_EN is asserted.

6.9.6

Dynamic Reconfiguration Interface

The following table provides interface timing information for the DRI, which is an embedded APB slave

interface within the FPGA fabric that does not use FPGA resources.

Table 142 • Dynamic Reconfiguration Interface Timing Characteristics

Unit

Max

Symbol

Parameter

MHz

200

FPD _PCLK

PCLK frequency

6.9.7

User Voltage Detector Characteristics

The following table provides the electrical characteristics of the VDD (1.0 V), VDD18, and VDD25 voltage

detectors. For proper operation of the voltage detectors, Vdd must be set to 1.0 V.

Table 143 • User Voltage Detector Electrical Characteristics

Condition

Unit

Max

Typ

Min

Parameter

Temp= –40 ºC to 1

00 ºC; VDD18 = 1.8

1.07

1.04

VDD_HIGH_DET

V ±5%; VDD25= 2.5

V ±5%

Temp= –40 ºC to 1

00 ºC; VDD = 1.0 V

1.96

1.9

VDD18_HIGH_DET

±3%; VDD25= 2.5 V

±5%

Temp= –40 ºC to 1

00 ºC; VDD = 1.0 V

2.74

2.66

VDD25_HIGH_DET

±3%; VDD18= 1.8 V

±5%

Temp= –40 ºC to 1

00 ºC; VDD18 = 1.8

0.915

0.945

VDD_LOW_DET

±5%; VDD25= 2.5 V

±5%

Temp= –40 ºC to 1

00 ºC; VDD = 1.0 ±3

1.57

1.62

VDD18_LOW_DET

109

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

AC Switching Characteristics

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