MPFS250T datasheet(116/128 Pages) MICROCHIP

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Table 145 • I/O-Related Supplies

I/O Power-Up Start Point (V)

Supply

0.85

VDDI

1.6

VDDAUX

There are no sequencing requirements for the power supplies. However, VDDI3 and must be valid at same

time as the main supplies. The other I/O supplies (VDDI, VDDAUX) have no effect on power-up of FPGA

fabric (that is, the fabric still powers up even if the I/O supplies of some I/O banks remain powered off).

6.10.4

User Design Dependence of Power-Up Times

Some phases of the device initialization are user design dependent, as the device automatically initializes

certain resources to user-specified configurations if those resources are used in the design. It is necessary

to compute the overall power-up to functional time by referencing the following tables and adding the

relevant phases, according to the design configuration. The following equation refers to timing parameters

specified in the above timing diagrams. Please note TPCIE , TXCVR, TLSRAM, and TUSRAM can be found in the

PolarFire SoC device power-up and resets user guide UG0725.

TPUFT = TFAB_READY(cold) + max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB)

TWRFT = TFAB_READY(warm) + max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB)

Note: TPCIE, TXCVR, TLSRAM, TUSRAM, and TCALIB are common to both cold and warm reset scenarios.

Auto-initialization of FPGA (if required) occurs in parallel with I/O calibration. The device may be considered

fully functional only when the later of these two activities has finished, which may be either one, depending

on the configuration, as may be calculated from the following tables. Note that I/O calibration may extend

beyond TPUFT (as I/O calibration process is independent of main device power-on and is instead dependent

on I/O bank supply relative power-on time and ramp times). The previous timing diagram for power-on

initialization shows the earliest that I/Os could be enabled, if the I/O power supplies are powered on before

or at the same time as the main supplies.

6.10.5

Cold Reset to Fabric and I/Os (Low Speed) Functional

The following table specifies the minimum, typical, and maximum times from the power supplies reaching

the above trip point levels until the FPGA fabric is operational and the FPGA IOs are functional for low-speed

(sub-400 MHz) operation.

Table 146 • Cold Boot

Unit

Max

Typ

Min

Power-On (Cold) Reset

to Fabric and I/O Oper-

ational

7.84

4.38

0.92

Time when input pins

start working – TIN_ACTIV-

E(cold)

7.84

4.38

0.92

Time when weak pull-

ups are enabled – TPU_

PD_ACTIVE(cold)

7.87

4.41

0.95

Time when fabric is op-

erational – TFAB_READY-

(cold)

112

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

AC Switching Characteristics

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