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XIO2000 数据表(PDF) 51 Page - Texas Instruments |
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XIO2000 数据表(HTML) 51 Page - Texas Instruments |
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51 / 150 page  Feature/Protocol Descriptions 39 November 2005 SCPS097B Table 3−15. Clocking In Low Power States CLOCK SOURCE D0/L0 D1/L1 D2/L1 D3/L2/L3 PCI express reference clock input (REFCLK) On On On On/Off PCI clock input (CLK) On Off Off Off Secondary PCI bus clock outputs (CLKOUT6:0) On On On On/Off The link power management (LPM) state machine manages active state power by monitoring the PCI Express transaction activity. If no transactions are pending and the transmitter has been idle for at least the minimum time required by the PCI Express Specification, then the LPM state machine transitions the link to either the L0s or L1 state. By reading the bridge’s L0s and L1 exit latency in the link capabilities register, the system software may make an informed decision relating to system performance versus power savings. The ASLPMC field in the link control register provides an L0s-only option, L1-only option, or both L0s and L1 option. Finally, the bridge generates the PM_Active_State_Nak Message if a PM_Active_State_Request_L1 DLLP is received on the PCI Express interface and the link cannot be transitioned to L1. |
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