XIO2000 datasheet(66/150 Pages) TI

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Classic PCI Configuration Space

November 2005

SCPS097B

Table 4−17. Bridge Control Register Description (Continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

ISA

ISA enable. This bit modifies the response by the bridge to ISA I/O addresses. This applies only to

I/O addresses that are enabled by the I/O base and I/O limit registers and are in the first 64 KB of

PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, then the bridge blocks any

forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each

1 KB block. In the opposite direction (secondary to primary), I/O transactions are forwarded if they

address the last 768 bytes in each 1K block.

0 = Forward downstream all I/O addresses in the address range defined by the I/O base and

I/O limit registers (default)

1 = Forward upstream ISA I/O addresses in the address range defined by the I/O base and I/O

limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each

1-KB block)

SERR_EN

SERR enable. This bit controls forwarding of system error events from the secondary interface to

the primary interface. The bridge forwards system error events when:

• This bit is set

• Bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set

• SERR is asserted on the secondary interface

0 = Disable the forwarding of system error events (default)

1 = Enable the forwarding of system error events

PERR_EN

Parity error response enable. Controls the bridge’s response to data, uncorrectable address, and

attribute errors on the secondary interface. Also, the bridge always forwards data with poisoning,

from conventional PCI to PCI Express on an uncorrectable conventional PCI data error, regardless

of the setting of this bit.

0 = Ignore uncorrectable address, attribute, and data errors on the secondary interface

(default)

1 = Enable uncorrectable address, attribute, and data error detection and reporting on the

secondary interface

4.30 Capability ID Register

This read-only register identifies the linked list item as the register for PCI power management. The register

returns 01h when read.

PCI register offset:

50h

Read-only

Default value:

01h

BIT NUMBER

RESET STATE

4.31 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

PCI register offset:

51h

Read-only

Default value:

60h

BIT NUMBER

RESET STATE

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