XIO2000 datasheet(78/150 Pages) TI

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Classic PCI Configuration Space

November 2005

SCPS097B

4.53 Link Control Register

The link control register controls link specific behavior. See Table 4−29 for a complete description of the

PCI register offset:

A0h

Read-only, Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 4−29. Link Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

RSVD

Reserved. Returns 00h when read.

Extended synch. This bit forces the bridge to extend the transmission of FTS ordered sets and an

extra TS2 when exiting from L1 prior to entering to L0.

0 = Normal synch (default)

1 = Extended synch

CCC

Common clock configuration. When this bit is set, it indicates that the bridge and the device at the

opposite end of the link are operating with a common clock source. A value of 0b indicates that the

bridge and the device at the opposite end of the link are operating with separate reference clock

sources. The bridge uses this common clock configuration information to report the L0s and L1 exit

latencies.

0 = Reference clock is asynchronous (default)

1 = Reference clock is common

Retrain link. This bit has no function and is read-only 0b.

Link disable. This bit has no function and is read-only 0b.

RCB

Read completion boundary. This bit is an indication of the RCB of the root complex. The state of

this bit has no affect on the bridge, since the RCB of the bridge is fixed at 128 bytes.

0 = 64 bytes (default)

1 = 128 bytes

RSVD

Reserved. Returns 0b when read.

1:0

ASLPMC

Active state link PM control. This field enables and disables the active state PM.

00 = Active state PM disabled (default)

01 = L0s entry enabled

10 = L1 entry enabled

11 = L0s and L1 entry enabled

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