XIO2000 datasheet(76/150 Pages) TI

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Classic PCI Configuration Space

November 2005

SCPS097B

Table 4−26. Device Control Register Description (Continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

URRE

Unsupported request reporting enable. If this bit is set, then the bridge sends an ERR_NONFATAL

message to the root complex when an unsupported request is received.

0 = Do not report unsupported requests to the root complex (default)

1 = Report unsupported requests to the root complex

FERE

Fatal error reporting enable. If this bit is set, then the bridge is enabled to send ERR_FATAL

messages to the root complex when a system error event occurs.

0 = Do not report fatal errors to the root complex (default)

1 = Report fatal errors to the root complex

NFERE

Nonfatal error reporting enable. If this bit is set, then the bridge is enabled to send

ERR_NONFATAL messages to the root complex when a system error event occurs.

0 = Do not report nonfatal errors to the root complex (default)

1 = Report nonfatal errors to the root complex

CERE

Correctable error reporting enable. If this bit is set, then the bridge is enabled to send ERR_COR

messages to the root complex when a system error event occurs.

0 = Do not report correctable errors to the root complex (default)

1 = Report correctable errors to the root complex

4.51 Device Status Register

The device status register provides PCI Express device specific information to the system. See Table 4−27

for a complete description of the register contents.

PCI register offset:

9Ah

Read-only

Default value:

0000h

BIT NUMBER

RESET STATE

Table 4−27. Device Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:6

RSVD

Reserved. Returns 00 0000 0000b when read.

PEND

Transaction pending. This bit is set when the bridge has issued a nonposted transaction that has

not been completed.

APD

AUX power detected. This bit indicates that AUX power is present.

0 = No AUX power detected

1 = AUX power detected

URD

RCU

Unsupported request detected. This bit is set by the bridge when an unsupported request is

received.

FED

RCU

Fatal error detected. This bit is set by the bridge when a fatal error is detected.

NFED

RCU

Nonfatal error detected. This bit is set by the bridge when a nonfatal error is detected.

CED

RCU

Correctable error detected. This bit is set by the bridge when a correctable error is detected.

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