XIO2000 datasheet(73/150 Pages) TI

73 / 150 page

Classic PCI Configuration Space

November 2005

SCPS097B

4.47 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

PCI register offset:

91h

Read-only

Default value:

00h

BIT NUMBER

RESET STATE

4.48 PCI Express Capabilities Register

This read-only register indicates the capabilities of the bridge related to PCI Express. See Table 4−24 for a

complete description of the register contents.

PCI register offset:

92h

Read-only

Default value:

0071h

BIT NUMBER

RESET STATE

Table 4−24. PCI Express Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:14

RSVD

Reserved. Returns 00b when read.

13:9

INT_NUM

Interrupt message number. This field is used for MSI support and is implemented as read-only

00000b in the bridge.

SLOT

Slot implemented. This bit is not valid for the bridge and is read-only 0b.

7:4

DEV_TYPE

Device/port type. This read-only field returns 7h indicating that the device is a PCI Express-to-PCI

bridge.

3:0

VERSION

Capability version. This field returns 1h indicating revision 1 of the PCI Express capability.

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