XIO2000 datasheet(52/150 Pages) TI

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Classic PCI Configuration Space

November 2005

SCPS097B

Classic PCI Configuration Space

The programming model of the XIO2000 PCI-Express to PCI bridge is compliant to the classic PCI-to-PCI

bridge programming model. The PCI configuration map uses the type 1 PCI bridge header.

All bits marked with a k are sticky bits and are reset by a global reset (GRST) or the internally-generated

power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST), a GRST, or the

internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST,

GRST, or the internally-generated power-on reset.

Table 4−1. Classic PCI Configuration Register Map

OFFSET

Device ID

Vendor ID

000h

Status

Command

004h

Class code

Revision ID

008h

BIST

Header type

Latency timer

Cache line size

00Ch

Device control base address

010h

Reserved

014h

Secondary latency timer

Subordinate bus number

Secondary bus number

Primary bus number

018h

Secondary status

I/O limit

I/O base

01Ch

Memory limit

Memory base

020h

Prefetchable memory limit

Prefetchable memory base

024h

Prefetchable base upper 32 bits

028h

Prefetchable limit upper 32 bits

02Ch

I/O limit upper 16 bits

I/O base upper 16 bits

030h

Reserved

Capabilities pointer

034h

Reserved

038h

Bridge control

Interrupt pin

Interrupt line

03Ch

Reserved

040h−04Ch

Power management capabilities

Next item pointer

PM CAP ID

050h

PM data

PMCSR_BSE

Power management CSR

054h

Reserved

058h−05Ch

MSI message control

Next item pointer

MSI CAP ID

060h

MSI message address

064h

MSI upper message address

068h

Reserved

MSI message data

06Ch

Reserved

070h−07Ch

Reserved

Next item pointer

SSID/SSVID CAP ID

080h

Subsystem ID†

Subsystem vendor ID†

084h

Reserved

088h−08Ch

PCI Express capabilities register

Next item pointer

PCI Express capability ID

090h

Device capabilities

094h

Device status

Device control

098h

Link capabilities

09Ch

Link status

Link control

0A0h

Reserved

0A4h−0ACh

Serial-bus control and

status†

Serial-bus slave address†

Serial-bus word address†

Serial-bus data†

0B0h

† One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

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