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XIO2000 数据表(PDF) 102 Page - Texas Instruments |
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XIO2000 数据表(HTML) 102 Page - Texas Instruments |
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102 / 150 page  PCI Express Extended Configuration Space 90 November 2005 SCPS097B 5.4 Uncorrectable Error Mask Register The uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5−3 for a complete description of the register contents. PCI Express extended register offset: 108h Register type: Read-only, Read/Write Default value: 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5−3. Uncorrectable Error Mask Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:21 RSVD R Reserved. Returns 000 0000 0000b when read. 20† UR_ERROR_MASK RW Unsupported request error mask 0 = Error condition is unmasked (default) 1 = Error condition is masked 19† ECRC_ERROR_MASK RW Extended CRC error mask 0 = Error condition is unmasked (default) 1 = Error condition is masked 18† MAL_TLP_MASK RW Malformed TLP mask 0 = Error condition is unmasked (default) 1 = Error condition is masked 17† RX_OVERFLOW_MASK RW Receiver overflow mask 0 = Error condition is unmasked (default) 1 = Error condition is masked 16† UNXP_CPL_MASK RW Unexpected completion mask 0 = Error condition is unmasked (default) 1 = Error condition is masked 15† CPL_ABORT_MASK RW Completer abort mask 0 = Error condition is unmasked (default) 1 = Error condition is masked 14† CPL_TIMEOUT_MASK RW Completion time-out mask 0 = Error condition is unmasked (default) 1 = Error condition is masked 13† FC_ERROR_MASK RW Flow control error mask 0 = Error condition is unmasked (default) 1 = Error condition is masked 12† PSN_TLP_MASK RW Poisoned TLP mask 0 = Error condition is unmasked (default) 1 = Error condition is masked 11:5 RSVD R Reserved. Returns 000 0000b when read. 4† DLL_ERROR_MASK RW Data link protocol error mask 0 = Error condition is unmasked (default) 1 = Error condition is masked 3:0 RSVD R Reserved. Returns 0h when read. † These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. |
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