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XIO2000 数据表(PDF) 109 Page - Texas Instruments |
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XIO2000 数据表(HTML) 109 Page - Texas Instruments |
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109 / 150 page  PCI Express Extended Configuration Space 97 November 2005 SCPS097B 5.12 Secondary Uncorrectable Error Severity Register The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is cleared, the corresponding error condition is identified as nonfatal. See Table 5−10 for a complete description of the register contents. PCI Express extended register offset: 134h Register type: Read-only, Read/Write Default value: 0000 1340h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 Table 5−10. Secondary Uncorrectable Error Severity Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:14 RSVD R Reserved. Returns 00 0000 0000 0000 0000b when read. 13† BRIDGE_ERROR_SEVR RW Internal bridge error. This severity bit is associated with a PCI-X error and has no effect on the bridge. 12† SERR_DETECT_SEVR RW SERR assertion detected 0 = Error condition is signaled using ERR_NONFATAL 1 = Error condition is signaled using ERR_FATAL (default) 11† PERR_DETECT_SEVR RW PERR assertion detected 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 10† DISCARD_TIMER_SEVR RW Delayed transaction discard timer expired 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 9† UNCOR_ADDR_SEVR RW Uncorrectable address error 0 = Error condition is signaled using ERR_NONFATAL 1 = Error condition is signaled using ERR_FATAL (default) 8† ATTR_ERROR_SEVR RW Uncorrectable attribute error. This severity bit is associated with a PCI-X error and has no effect on the bridge. 7† UNCOR_DATA_SEVR RW Uncorrectable data error 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 6† SC_MSG_DATA_SEVR RW Uncorrectable split completion message data error. This severity bit is associated with a PCI-X error and has no effect on the bridge. 5† SC_ERROR_SEVR RW Unexpected split completion error. This severity bit is associated with a PCI-X error and has no effect on the bridge. 4 RSVD R Reserved. Returns 0b when read. 3† MASTER_ABORT_SEVR RW Received master abort 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 2† TARGET_ABORT_SEVR RW Received target abort 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 1† SC_MSTR_ABORT_SEVR RW Master abort on split completion. This severity bit is associated with a PCI-X error and has no effect on the bridge. 0 RSVD R Reserved. Returns 0b when read. † These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. |
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