CS5535 datasheet(335/555 Pages) NSC

335 / 555 page

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PIC Register Descriptions (Continued)

5.9.1.4

IRQ Mapper LPC Mask (PIC_IRQM_LPC)

5.9.1.5

IRQ Mapper Extended Interrupt Request Status Low (PIC_XIRR_STS_LOW)

15:0

PRIM[15:0]_MSK

Primary Inputs [15:0] Mask. Bits [15:0] correspond to Primary Inputs [15:0], bit 2 is

reserved (i.e., no IRQ2).

0: Mask the interrupt source.

1: Do not mask the interrupt source.

For Primary Inputs [15:0] sources, see Table 4-12 on page 104.

MSR Address

51400025h

PIC I/O Offset

14h

Type

R/W

Reset Value

00000000h

PIC_IRQM_LPC Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

RSVD

PIC_IRQM_LPC Bit Descriptions

Bit

Name

Description

31:16

RSVD

Reserved. Set to 0.

15:0

LPC[15:0]_EN

LPC Inputs [15:0] Enable. Bits [15:0] correspond to LPC Inputs [15:0], bit 2 is don’t

care (i.e., no IRQ2).

0: Disable interrupt source.

1: Enable interrupt source.

For LPC Inputs [15:0] sources, see Table 4-12 on page 104.

MSR Address

51400026h

PIC I/O Offset

18h

Type

Reset Value

xxxxxxxxh

PIC_XIRR_STS_LOW Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

IG7_STS

IG6_STS

IG5_STS

IG4_STS

IG3_STS

IG2_

STS

RSVD

IG1_STS

RSVD

IG0_

STS

PIC_IRQM_PRIM Bit Descriptions

Bit

Name

Description

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