CS5535 datasheet(338/555 Pages) NSC

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PIC Register Descriptions (Continued)

5.9.1.7

PIC Shadow (PIC_SHDW)

3:0

IG8_STS

Group 8 Interrupt Status. Reports the status of the four interrupts in this group.

bit 0: Primary Input 8.

bit 1: LPC Input 8.

bit 2: Unrestricted Y Input 8.

bit 3: Unrestricted Z Input8.

MSR Address

51400034h

Type

Reset Value

xxh

PIC_SHDW Register Map

PIC_SHDW

PIC_SHDW Bit Descriptions

Bit

Name

Description

7:0

PIT_SHDW (RO)

PIC Shadow (Read Only). This 8-bit port sequences through the following list of shad-

owed Programmable Interrupt Controller registers. At power on, a pointer starts at the

first register in the list and consecutively reads incrementally through it. A write to this

sequence contains the last data written to that location.

The read sequence for this register is:

PIC1 ICW1.

PIC1 ICW2.

PIC1 ICW3.

PIC1 ICW4 - Bits [7:5] of ICW4 are always 0.

PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 (Note 1).

PIC1 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1.

PIC2 ICW1.

PIC2 ICW2.

PIC2 ICW3.

10. PIC2 ICW4 - Bits [7:5] of ICW4 are always 0.

11. PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (Note 1).

12. PIC2 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1.

Note 1. To restore OCW2 to shadow register value, write the appropriate address twice. First with the shadow register val-

ue, then with the shadow register value ORed with C0h.

PIC_XIRR_STS_HIGH Bit Descriptions (Continued)

Bit

Name

Description

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