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PIC Register Descriptions (Continued)

5.9.2

PIC Native Registers

There are two separate PIC sub-blocks in the CS5535, connected in a cascaded arrangement, as is required for a PC-com-

patible system. Each PIC has its own native register set, apart from the MSR registers (unique to the CS5535 architecture),

which are common.

The master PIC occupies I/O Addresses 020h and 021h, and manages IRQ signals IRQ0 through IRQ7, with IRQ2 claimed

as the cascade input for the slave PIC. The slave PIC occupies I/O Addresses 0A0h and 0A1h, and manages IRQ signals

IRQ8 through IRQ15. In this description, the two addresses of a PIC are called the Even address (A[0] = 0) and the Odd

address (A[0] = 1).

The PIC register set addressing is often confusing due to some very severe constraints the PIC had in its earliest history.

When it was a separate chip, the package pinout limited it to only one address line. To make up for this, two bits of the data

written (bits 3 and 4) sometimes serve an addressing function to select registers.

The chip functions in two fundamental modes with respect to register accesses: it is either in Operation Mode (normal oper-

ation), or it is in Initialization Mode (being initialized). Different sets of registers are selected in each mode.

Operation Mode

When the PIC is in Operation Mode, a set of registers may be accessed, called the Operation Command Words (OCWs).

These are:

• OCW1: The Interrupt Mask register (IMR), may be read or written at any time except during Initialization.

• OCW2: A write-only register that is given commands from software. For example, the End of Interrupt command is

written here at the end of interrupt service to terminate the blocking of interrupts on the basis of priority.

• OCW3: A write-only register that is given a different set of commands from software. For example, it is through this

— IRR: Interrupt Request Register -- shows those IRQs with pending interrupts that have not yet received an Interrupt

Acknowledge from the CPU.

— ISR: In-Service Register -- shows those IRQs that have received Interrupt Acknowledge, but whose interrupt service

routines have not yet completed.

Initialization Mode

The PIC is placed into its Initialization Mode by a write of a reserved value (xxx1xxxx) to the even-numbered address (mas-

ter 0020h / slave 00A0h). This is the first of a sequence of writes to a special set of Initialization Control Word registers

(ICW1, ICW2, ICW3 and ICW4) that hold permanent settings and are normally touched only while the operating system is

booting.

5.9.2.1

Writing to the Even Address

Other write and read accesses do not depend directly on this form of addressing.

Writing to the Odd Address

Data Bit 4

Data Bit 3

Access Performed

In Operation Mode, writes to OCW2, asserting a routine command.

In Operation Mode, writes to OCW3, asserting a special or diagnostic command.

Commands written to OCW3 may request to examine an internal PIC register; if so, this

(even) address must be immediately read to retrieve the requested value and terminate the

command. See "Reading from the Even Address" below.

0 or 1

Triggers Initialization Mode and writes to ICW1. Bit 3 is used as a data bit in this case.

Operation Mode:

Writes to the Interrupt Mask Register: OCW1.

Initialization Mode:

Three successive writes to this address must immediately follow the write to ICW1 (above),

before any other accesses are performed to the PIC. These writes load ICW2, ICW3 and

ICW4 in succession, after which the PIC automatically transitions to Operation Mode.

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