CS5535 datasheet(340/555 Pages) NSC

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340

Revision 0.8

PIC Register Descriptions (Continued)

Reading from the Even Address

(Operation Mode only: the initialization sequence does not involve reading.)

Reads from this address are generally for special or diagnostic purposes. The read must be preceded by writing a com-

mand to OCW3 (above), to select an internal register to read. This will be one of:

• Register IRR: Interrupt Request Register

• Register ISR: In-Service Register

(Another register, "POLL", historically part of the PIC architecture, is not provided in the CS5535.)

Following that command, the read here will return the requested value.

Reading from the Odd Address

(Operation Mode only: the Initialization sequence does not involve reading.)

Always reads from the Interrupt Mask Register: OCW1.

Associated External Registers

Two additional registers, outside the addresses of the PICs themselves, have been added in South Bridge products to allow

individual control of which IRQs are level sensitive vs. edge sensitive. These registers are:

These are directly addressable for read or write at any time.

5.9.2.2

Initialization Command Word 1 (PIC_ICW1)

Name

I/O Address

IRQs Controlled

INT_SEL1

04D0h

IRQ1, IRQ3-7

INT_SEL2

04D1h

IRQ8-15

I/O Port

Master: 020h

Slave:

0A0h

Type

Reset Value

00h

PIC_ICW1 Register Map

RSVD

TRIGGER

RSVD

PIC_ICW1 Bit Descriptions

Bit

Name

Description

7:5

RSVD

Reserved. Write to 0.

Write to 1. Write to 1 to write ICW1 and enter Initialization Mode. (See Section 5.9.2

"PIC Native Registers" on page 339.)

3TRIGGER

Trigger Mode.

0: Edge.

1: Level.

RSVD

Reserved. Write to 0.

RSVD

Reserved. Write to 0.

RSVD

Reserved. Write to 1.

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