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CS5535 数据表(PDF) 345 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 345 Page - National Semiconductor (TI) |
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345 / 555 page  Revision 0.8 345 www.national.com PIC Register Descriptions (Continued) 5.9.2.11 Interrupt Edge/Level Select 1 (PIC_INT_SEL1) PIC_ISR Bit Descriptions Bit Name Description 7 IRQ7_15IS IRQ7 / IRQ15 In-Service. 0: No; 1: Yes. 6 IRQ6_14IS IRQ6 / IRQ14 In-Service. 0: No; 1: Yes. 5 IRQ5_13IS IRQ5 / IRQ13 In-Service. 0: No; 1: Yes. 4 IRQ4_12IS IRQ4 / IRQ12 In-Service. 0: No; 1: Yes. 3 IRQ3_11IS IRQ3 / IRQ11 In-Service. 0: No; 1: Yes. 2 IRQ2_10IS IRQ2 / IRQ10 In-Service. 0: No; 1: Yes. 1 IRQ1_9IS IRQ1 / IRQ9 In-Service. 0: No; 1: Yes. 0 IRQ0_8IS IRQ0 / IRQ8 In-Service. 0: No; 1: Yes. I/O Port 4D0h Type R/W Reset Value 00h PIC_INT_SEL1 Register Map 76 54 32 10 IRQ7_SEL IRQ6_SEL IRQ5_SEL IRQ4_SEL IRQ3_SEL RSVD IRQ1_SEL RSVD PIC_INT_SEL1 Bit Descriptions Bit Name Description 7 IRQ7_SEL IRQ7 Edge or Level Select. Selects PIC IRQ7 sensitivity configuration. 0: Edge; 1: Level. (Note 1) Note 1. If ICW1 bit 3 in the PIC is set as level, it overrides the settings of this bit. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). 6 IRQ6_SEL IRQ6 Edge or Level Select. Selects PIC IRQ6 sensitivity configuration. 0: Edge; 1: Level. (Note 1) 5 IRQ5_SEL IRQ5 Edge or Level Select. Selects PIC IRQ5 sensitivity configuration. 0: Edge; 1: Level. (Note 1) 4 IRQ4_SEL IRQ4 Edge or Level Select. Selects PIC IRQ4 sensitivity configuration. 0: Edge; 1: Level. (Note 1) 3 IRQ3_SEL IRQ3 Edge or Level Select. Selects PIC IRQ7 sensitivity configuration. 0: Edge; 1: Level. (Note 1) 2 RSVD Reserved. Write to 0. 1 IRQ1_SEL IRQ1 Edge or Level Select. Selects PIC IRQ1 sensitivity configuration. 0: Edge; 1: Level. (Note 1) 0 RSVD Reserved. Write to 0. |
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