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CS5535 数据表(PDF) 346 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 346 Page - National Semiconductor (TI) |
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346 / 555 page ![]() www.national.com 346 Revision 0.8 PIC Register Descriptions (Continued) 5.9.2.12 Interrupt Edge/Level Select 2 (PIC_INT_SEL2) I/O Port 4D1h Type R/W Reset Value 00h PIC_INT_SEL2 Register Map 76 54 32 10 IRQ7_SEL IRQ6_SEL IRQ5_SEL IRQ4_SEL IRQ3_SEL RSVD IRQ1_SEL RSVD PIC_INT_SEL2 Bit Descriptions Bit Name Description 7 IRQ15_SEL IRQ15 Edge or Level Select. Selects PIC IRQ15 sensitivity configuration. 0: Edge; 1: Level. (Note 1) Note 1. If ICW1 bit 3 in the PIC is set as level, it overrides the settings of this bit. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). 6 IRQ14_SEL IRQ14 Edge or Level Select. Selects PIC IRQ14 sensitivity configuration. 0: Edge; 1: Level. (Note 1) 5 RSVD Reserved. Write to 0. 4 IRQ12_SEL IRQ12 Edge or Level Select. Selects PIC IRQ12 sensitivity configuration. 0: Edge; 1: Level. (Note 1) 3 IRQ11_SEL IRQ11 Edge or Level Select. Selects PIC IRQ11 sensitivity configuration. 0: Edge; 1: Level. (Note 1) 2 IRQ10_SEL IRQ10 Edge or Level Select. Selects PIC IRQ10 sensitivity configuration. 0: Edge; 1: Level. (Note 1) 1 IRQ9_SEL IRQ9 Edge or Level Select. Selects PIC IRQ9 sensitivity configuration. 0: Edge; 1: Level. (Note 1) 0 RSVD Reserved. Write to 0. |
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