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CS5535 数据表(PDF) 360 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 360 Page - National Semiconductor (TI) |
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360 / 555 page  www.national.com 360 Revision 0.8 5.12 UART AND IR PORT REGISTER DESCRIPTIONS The registers for the UART/IR Controller are divided into three sets: • Standard GeodeLink Device MSRs (Shared with DIVIL, see Section 5.6.1 on page 299.) • UART/IR Controller Specific MSRs • UART/IR Controller Native Registers The MSRs are accessed via the RDMSR and WRMSR pro- cessor instructions. The MSR address is derived from the perspective of the CPU Core. See Section 3.2 "CS5535 MSR Addressing" on page 53 for more details on MSR addressing. All MSRs are 64 bits, however, the UART/IR Controller Specific MSRs (summarized in Table 5-28) are called out as 8 bits. The UART/IR Controller treats writes to the upper 56 bits (i.e., bits [63:8]) of the 64-bit MSRs as don’t cares and always returns 0 on these bits. The UART/IR Controller Native register set consists of eight register banks, each containing eight registers, to control UART operation. All registers use the same 8-byte address space to indicate I/O Offsets 00h-07h. The Native registers are accessed via Banks 0 through 7 as I/O Off- sets. See MSR_LEG_IO (MSR 51400014h) bits [22:20] and bits [18:16] for setting base address. Each bank and its offsets are summarized in Table 5-29. The register summary tables include reset values and page references where the bit descriptions are provided. Table 5-28. UART/IR Controller Specific MSRs Summary MSR Address Type Register Name Reset Value Reference 51400038h R/W UART1 Primary Dongle and Modem Interface (UART[1]_MOD) 0xh Page 363 51400039h R/W UART1 Secondary Dongle and Status (UART[1]_DONG) xxh Page 364 5140003Ah R/W UART1 Interface Configuration (UART[1]_CONF) 42h Page 365 5140003Bh R/W UART1 Reserved MSR (UART[1]_RSVD_MSR) - Reads return 0; writes have no effect. 00h --- 5140003Ch R/W UART2 Primary Dongle and Modem Interface (UART[2]_MOD) 0xh Page 363 5140003Dh R/W UART2 Secondary Dongle and Status (UART[2]_DONG) xxh Page 364 5140003Eh R/W UART2 Interface Configuration (UART[2]_CONF) 42h Page 365 5140003Fh R/W UART2 Reserved MSR (UART[2]_RSVD_MSR) - Reads return 0; writes have no effect. 00h --- Table 5-29. UART/IR Controller Native Registers Summary I/O Offset Type Register Name Reset Value Reference Bank 0 00h RO Receive Data Port (RXD) xxh Page 367 WO Transmit Data Port (TXD) xxh Page 367 01h R/W Interrupt Enable Register (IER) 00h Page 368 02h RO Event Identification Register (EIR) Extended Mode: 22h Page 369 Non-Extended Mode: 01h Page 371 WO FIFO Control Register (FCR) 00h Page 372 03h WO Link Control Register (LCR) 00h Page 373 R/W Bank Select Register (BSR) 00h Page 375 04h R/W Modem/Mode Control Register (MCR) 00h Page 376 05h RO Link Status Register (LSR) 60h Page 377 06h RO Modem Status Register (MSR) x0h Page 379 |
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