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CS5535 数据表(PDF) 357 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CS5535
功能描述  Geode??CS5535 I/O Companion Multi-Function South Bridge
PDF  555 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CS5535 数据表(HTML) 357 Page - National Semiconductor (TI)

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SMB Controller Register Descriptions (Continued)
5.11.1.4
SMB Control 1 (SMB_CTRL1)
This register configures and controls the SMB functional block. It maintains the current SMB status and controls several
SMB functions. On reset and when the SMB is disabled, the non-reserved bits of SMB_CTRL1 are cleared.
SMB I/O Offset
03h
Type
R/W
Reset Value
00h
SMB_CTRL1 Register Map
76
54
32
10
STASTRE
NMINTE
GCMEN
ACK
RSVD
INTEN
STOP
START
SMB_CTRL1 Bit Descriptions
Bit
Name
Description
7
STASTRE
Stall After Start Enable.
0: When cleared, STASTR (SMB I/O Offset 01h[3]) can not be set. However, if
STASTR is set, clearing STASTRE will not clear STASTR.
1: Stall after start mechanism enabled, and SMB stalls the bus after the address byte.
6NMINTE
New Match Interrupt Enable.
0: No interrupt issued on a new match.
1: Interrupt issued on a new match only if INTEN (bit 2) is set.
5GCMEN
Global Call Match Enable.
0: SMB not responding to global call.
1: Global call match enabled.
4ACK
Receive Acknowledge. This bit is ignored in transmit mode. When the device acts as
a receiver (slave or master), this bit holds the transmitting instruction that is transmitted
during the next acknowledge cycle.
0: Cleared after acknowledge cycle.
1: Negative acknowledge issued on next received byte.
3
RSVD
Reserved. Reads return 0; writes have no effect.
2INTEN
Interrupt Enable.
0: SMB interrupt disabled.
1: SMB interrupt enabled. An interrupt is generated in response to one of the following
events:
-Detection of an address match (NMATCH, SMB I/O Offset 01h[2] = 1) and NMINTE
(bit 6) = 1.
-Receipt of bus error (BER, SMB I/O Offset 01h[5] = 1).
-Receipt of Negative Acknowledge after sending a byte (NEGACK, SMB I/O Offset
01h[4] = 1).
-Acknowledge of each transaction (same as the hardware set of the SDAST bit,
SMB I/O Offset 01h[6]) when DMA not enabled.
-In master mode if STASTRE = 1 (SMB I/O Offset 03h[7]), after a successful start
(STASTR = 1, SMB I/O Offset 01h[3]).
-Detection of a Stop condition while in slave mode (SLVSTP = 1, SMB I/O Offset
01h[7]).



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