CS5535 datasheet(354/555 Pages) NSC

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Revision 0.8

SMB Controller Register Descriptions (Continued)

5.11.1 SMB Native Registers

5.11.1.1

SMB Serial Data (SMB_SDA)

5.11.1.2

SMB Status (SMB_STS)

This is a read/write register with a special clear. Some of its bits may be cleared by software, as described in the table

below. This register maintains the current SMB status. On reset, and when the SMB is disabled, SMBST is cleared (00h).

SMB I/O Offset

00h

Type

R/W

Reset Value

00h

SMB_SDA Register Map

SMBSDA

SMB_SDA Bit Descriptions

Bit

Name

Description

7:0

SMBSDA

SMB Serial Data. This shift register is used to transmit and receive data. The most sig-

nificant bit is transmitted (received) first, and the least significant bit is transmitted last.

Reading or writing to the SMBSDA register is allowed only when the SDAST bit (SMB

I/O Offset 01h[6]) is set, or for repeated starts after setting the START bit (SMB I/O Off-

set 03h[0]). Any attempt to access the register in other cases may produce unpredict-

able results.

SMB I/O Offset

01h

Type

R/W

Reset Value

00h

SMB_STS Register Map

SLVSTP

SDAST

BER

NEGACK

STASTR

NMATCH

MASTER

XMIT

SMB_STS Bit Descriptions

Bit

Name

Description

SLVSTP (R/W1C)

Slave Stop (Read/Write 1 to Clear). Writing 0 to SLVSTP is ignored.

0: Writing 1 or SMB disabled.

1: Stop condition detected after a slave transfer in which MATCH (SMB I/O Offset

02h[2]) or GCMATCH (SMB I/O Offset 02h[3]) was set.

SDAST (RO)

SMB_DATA Status (Read Only).

0: Reading from SMBSDA (SMB I/O Offset 00h) during a receive, or when writing to it

during a transmit. When START (SMB I/O Offset 03h[0]) is set, reading SMBSDA

does not clear SDAST; enabling the SMB to send a repeated start in master receive

mode.

1: SMBSDA awaiting data (transmit - master or slave) or holds data that should be

read (receive - master or slave).

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