CS5535 datasheet(352/555 Pages) NSC

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352

Revision 0.8

KEL Register Descriptions (Continued)

5.10.2.5

Port A (KEL_PORTA)

Bit 4 of KELX_CTL (MSR 5140001Fh[4]) is the Port A Enable bit. It must be set to 1 to enable access to this register; oth-

erwise, Port A accesses are directed to the LPC bus where a Port A register may exist in a SuperI/O device.

I/O Port

092h

Type

R/W

Reset Value

00h

KEL_PORTA Register Map

RSVD

A20_MASK

SYSR

KEL_PORTA Bit Descriptions

Bit

Name

Description

7:2

RSVD

Reserved. Writes have no effect; reads return 0.

A20_MASK

A20 Mask. This bit is necessary for older programs that require Port A Address bit 20

emulation. It requires ASMIs to be enabled in order for software to recognize the chang-

ing of this bit, and subsequent proper emulation of the A20 address bit (see

PORTA_A20_ASMI_EN bit in DIVIL GLD_MSR_SMI, MSR 51400002h[6], for ASMI

enabling details). Anytime this bit is changed an ASMI is generated.

If this bit is 1 and a 0 is written, and ASMI generation is enabled, then proper VSA oper-

ation causes a rollover of address from A[19:0] = all 1s, to A[19:0] = all 0s. Address bit

A20 is 0.

If this bit is 0 and a 1 is written, and ASMI generation is enabled, then no legacy rollover

occurs from address [19:0] = all 1s. The next incremental address is A20 = 1 and

A[19:0] = all 0.

SYSR

Legacy System Reset. Writing a 1 to this bit causes a system soft reset (INIT) that will

only happen if ASMIs are enabled (see PORTA_INIT_ASMI_EN bit in DIVIL

GLD_MSR_SMI, MSR 51400002h[7], for ASMI enabling details). Writing a 0 to this bit

has no effect. This bit always reads as 0.

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