CS5535 datasheet(351/555 Pages) NSC

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KEL Register Descriptions (Continued)

5.10.2.4

KEL HCE Status (KEL_HCE_STS)

The contents of the HCE_Status register are returned on an I/O read of I/O Port 064h when emulation is enabled. Reads

and writes of I/O Port 060h and writes to I/O Port 064h can cause changes in this register. Emulation software can directly

access this register through its memory address in the KEL’s operational register space. Accessing this register through its

memory address produces no side effects.

KEL Memory Offset 10Ch

Type

R/W

Reset Value

00000000h

KEL_HCE_STS Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

RSVD

KEL_HCE_STS Bit Descriptions

Bit

Name

Description

31:8

RSVD

Reserved. Writes have no effect; reads return 0.

7Parity

Parity. Indicates parity error on keyboard/mouse data. The value of this bit is only

changed by a direct write to this register.

Timeout

Timeout. Used to indicate a timeout. The value of this bit is only changed by a direct

write to this register.

AuxOutputFull

Auxiliary Output Full. IRQ12 is asserted whenever this bit is set, OutputFull is set,

and IRQEn is set. The value of this bit is only changed by a direct write to this register.

InhibitSwitch

Inhibit Switch. This bit reflects the state of the keyboard inhibit switch and is set if the

keyboard is NOT inhibited.

3CmdData

Command Data. The KEL clears this bit on an I/O write to I/O Port 60h and sets it on

an I/O write to I/O Port 064h.

2Flag

Flag. Nominally used as a system flag by software to indicate a warm or cold boot.

InputFull

Input Full. Except for the case of a A20 sequence, this bit is set on an I/O write to I/O

Port 060h or 064h. While this bit is set and emulation is enabled, an emulation interrupt

occurs. This bit can only be cleared by a direct write of 0.

OutputFull

Output Full. The KEL clears this bit on a read of I/O Port 060h. If IRQEn is set and

AuxOutputFull is clear, then an IRQ1 is generated as long as this bit is set. If IRQEn is

set and AuxOutputFull is set, then an IRQ12 is generated as long as this bit is set. If

this bit is clear and CharacterPending in HCE_Control is set, an emulation interrupt

occurs. This bit can only be set by a direct write of this register.

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