CS5535 datasheet(372/555 Pages) NSC

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372

Revision 0.8

UART/IR Controller Register Descriptions (Continued)

FIFO Control Register (FCR)

The FIFO Control Register (FCR) is used to enable the FIFOs, clear the FIFOs and set the interrupt threshold levels for the

RX_FIFO and TX_FIFO. FCR can be read through SH_FCR in Bank 3, I/O Offset 02h (see Section 5.12.6.3 on page 388).

I/O Offset

02h

Type

Reset Value

00h

FCR Register Map

RXFTH

TXFTH

RSVD

TXSR

RXSR

FIFO_EN

FCR Bit Descriptions

Bit

Name

Description

7:6

RXFTH

RX_FIFO Interrupt Threshold Level. These bits select the RX_FIFO interrupt threshold

level. An interrupt is generated when the level of data in the RX_FIFO is equal to or above

the encoded threshold.

RX_FIFO Interrupt Threshold Level

(16-Level FIFO)

(32-Level FIFO)

00:

1 (Default)

01:

10:

11:

5:4

TXFTH[1:0]

TX_FIFO Interrupt Threshold Level. In non-extended modes, these bits have no effect.

In extended modes, these bits select the TX_FIFO interrupt threshold level. An interrupt is

generated when the level of data in the TX_FIFO drops below the encoded threshold.

TX_FIFO Interrupt Threshold Level

(16-Level FIFO)

(32-Level FIFO)

00:

1 (Default)

01:

10:

11:

RSVD

Reserved. Write to 0.

TXSR

Transmitter Soft Reset. Writing a 1 to this bit generates a transmitter soft reset that clears

the TX_FIFO and the transmitter logic. This bit is automatically cleared by the hardware.

RXSR

Receiver Soft Reset. Writing a 1 to this bit generates a receiver soft reset that clears the

RX_FIFO and the receiver logic. This bit is automatically cleared by the hardware.

0FIFO_EN

FIFO_EN (FIFO Enable). When set to 1, this bit enables both the TX_FIFO and

RX_FIFOs. Resetting this bit clears both FIFOs. In CEIR mode, the FIFOs are always

enabled and the setting of this bit is ignored.

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