 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
CS5535 数据表(PDF) 369 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
CS5535 数据表(HTML) 369 Page - National Semiconductor (TI) |
|
|
369 / 555 page  Revision 0.8 369 www.national.com UART/IR Controller Register Descriptions (Continued) IER, Non-Extended Mode: UART, SIR or Sharp-IR (EXCR1.EXT_SL = 0) Upon reset, the IER supports UART, SIR and Sharp-IR in non-extended modes. 5.12.3.3 Event Identification (EIR)/FIFO Control Registers (FCR) The Event Identification Register (EIR) is a read-only register and shares the same address as the write-only FIFO Control Register (FCR). Event Identification Register (EIR) The EIR indicates the interrupt source, and operates in two modes, non-extended mode (EXT_SL of the EXCR1 register = 0), and extended mode (EXT_SL of the EXCR1 register = 1) (Bank 2, I/O Offset 02h[0]). In non-extended mode (default), this register functions the same as in the 16550 mode. EIR, Extended Mode (EXCR1.EXT_SL = 1) In extended mode, each of the previously prioritized and encoded interrupt sources is broken down into individual bits. Each bit in this register acts as an interrupt pending flag, and is set to 1 when the corresponding event has occurred or is pending, regardless of the IER register bit setting. When this register is read, the DMA event (bit 4) is cleared if an 8237 type DMA is used. All other bits are cleared when the corresponding interrupts are acknowledged, by reading the relevant register (e.g., reading the MSR register clears MS_EV). IER Non-Extended Mode Register Map 76 54 32 10 RSVD MS_IE LS_IE TXLDL_IE RXHDL_IE IER Non-Extended Mode Bit Descriptions Bit Name Description 7:4 RSVD Reserved. Write as 0. 3MS_IE Modem Status Interrupt Enable. Setting this bit to 1 enables the interrupts on modem status events. (EIR bits [3:0] are 0000.) 2LS_IE Link Status Interrupt Enable. Setting this bit to 1 enables interrupts on Link Status events. (EIR bits [3:0] are 0110) 1 TXLDL_IE Transmitter Low Data Level Interrupt Enable. Setting this bit to 1 enables interrupts on transmitter low data level events. (EIR bits [3:0] are 0010.) 0 RXHDL_IE Receiver High Data Level Interrupt Enable. Setting this bit to 1 enables interrupts on receiver high data level, or RX_FIFO timeout events. (EIR bits [3:0] are 0100 or 1100.) I/O Offset 02h Type RO Reset Value Extended Mode: 22h Non-Extended Mode: 01h EIR Extended Mode Register Map 76 54 32 10 RSVD TXEMP_EV DMA_EV MS_EV LS_EV/TXHLT_ EV TXLDL_EV RXHDL_EV |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
